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PIC16F1823 test program / template


All this does is flash LEDs on PORTA pins 0,1,2,4 and 5. It also changes the oscillator frequency to 31.25KHz.
The MCLR pin should be connected to 5V with a 1K resistor, and a 100nF capacitor should be between VDD and VSS.
I haven't actually got a chip to test it on yet, but it works fine in the simulator.


The source code in assembler(.asm)



	list		p=16f1823      ; list directive to define processor
	#include	 ; processor specific variable definitions

;------------------------------------------------------------------------------
;
; CONFIGURATION WORD SETUP
;
; The 'CONFIG' directive is used to embed the configuration word within the 
; .asm file. The lables following the directive are located in the respective 
; .inc file.  See the data sheet for additional information on configuration 
; word settings.
;
;------------------------------------------------------------------------------    

    __CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF
    __CONFIG _CONFIG2, _WRT_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_19 & _LVP_OFF

;------------------------------------------------------------------------------
; VARIABLE DEFINITIONS
;
; Available Data Memory divided into Bank 0-15.  Each Bank may contain 
; Special Function Registers, General Purpose Registers, and Access RAM 
;
;------------------------------------------------------------------------------

    CBLOCK 0x20 ; Define GPR variable register locations
        d1  ; User variables allocated contiguously
        d2  ; 
        MYVAR3  ; 
    ENDC



;------------------------------------------------------------------------------
; EEPROM INITIALIZATION
;
; The 16F1823 has 256 bytes of non-volatile EEPROM, starting at address 0xF000
; 
;------------------------------------------------------------------------------

DATAEE    ORG  0xF000
    DE    "MCHP"  ; Place 'M' 'C' 'H' 'P' at address 0,1,2,3

;------------------------------------------------------------------------------
; RESET VECTOR
;------------------------------------------------------------------------------

    ORG     0x0000            ; processor reset vector
    GOTO    init             ; When using debug header, first inst.
                              ; may be passed over by ICD2.  

;------------------------------------------------------------------------------
; INTERRUPT SERVICE ROUTINE
;------------------------------------------------------------------------------

    ORG      0x0004
	banksel PORTA				;remove if not required (could be in any bank when interrupt happens)
;------------------------------------------------------------------------------
; USER INTERRUPT SERVICE ROUTINE GOES HERE
;------------------------------------------------------------------------------

; Note the 16F1933 family automatically handles context restoration for 
; W, STATUS, BSR, FSR, and PCLATH where previous templates for 16F families
; required manual restoration

    RETFIE                    ; return from interrupt
    
init
	banksel OSCCON
	movlw b'00010010'			;31.25kHz MFosc
	movwf OSCCON
	banksel PORTA

	BANKSEL PORTA ;					;set up port A
	CLRF PORTA ;Init PORTA
	BANKSEL LATA ;Data Latch
	CLRF LATA ;
	BANKSEL ANSELA ;
	CLRF ANSELA ;digital I/O
	BANKSEL TRISA ;
	MOVLW B'00001000' ;Set RA<3> as input
	MOVWF TRISA 		;and set RA<2:0> and RA<5:4> as outputs
	banksel PORTA

	BANKSEL PORTC ;					;set up port C
	CLRF PORTC ;Init PORTC
	BANKSEL LATC ;Data Latch
	CLRF LATC ;
	BANKSEL ANSELC
	CLRF ANSELC ;Make RC<5:0> digital
	BANKSEL TRISC ;
	MOVLW B'00000000'			;Set all outputs
	MOVWF TRISC ;
	banksel PORTA

start
	BANKSEL LATA
	movlw 0xFF
	movwf LATA					;write to LATA instead of PORTA to avoid problems
	banksel PORTA
	call delay1sec
	BANKSEL LATA
	movlw 0x00
	movwf LATA
	banksel PORTA
	call delay1sec

    GOTO start





; Delay = 1 seconds
; Clock frequency = 0.03125 MHz

; Actual delay = 1.000064 seconds = 7813 cycles
; Error = -0.0064 %



delay1sec
			;7808 cycles
	movlw	0x19
	movwf	d1
	movlw	0x07
	movwf	d2
delay1sec_0
	decfsz	d1, f
	goto	$+2
	decfsz	d2, f
	goto	delay1sec_0

			;1 cycle
	nop

			;4 cycles (including call)
	return


    END